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KAIST Device-to-System Integration Lab (DSIL)

Our lab aims to develop core semiconductor technologies for next-generation AI hardware systems. To achieve this, we take a multidisciplinary approach—centered on Electrical Engineering and integrated with Mechanical Engineering, Materials Science, and Chemical Engineering—to research integrated semiconductor technologies that connect devices, packaging, and systems.

Our research fields cover a wide range of areas, including:

  • Logic and memory transistors (2D TMD, CNT for logic / oxide semiconductors for DRAM)
  • Monolithic 3D (M3D) systems (3D IC design and PPA evaluation)
  • Advanced semiconductor packaging
  • Heterogeneous multi-chip systems (package-level digital architecture, system evaluation)

Contact Us

Currently, we give priority to applicants for the Ph.D. or MS-Ph.D. integrated programs who can make a long-term commitment. If you are interested, please send your CV, academic transcripts, and research activity materials (papers, projects, etc.) to my email (jmkwon@kaist.ac.kr).

Latest News

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  • Title: Vertical-Die (V-die) 3.5D Integration for Cool Ultrahigh-Bandwidth Memory Systems

A paper with Heesoo Yang (integrated M.S./Ph.D., 2nd year) and Hyeongjun Kim (integrated M.S./Ph.D., 2nd year) as co-first authors has been accepted to the IEEE Symposium on VLSI Technology and Circuits (VLSI) 2026, one of the most prestigious international conferences on integrated devices and circuits. The work was carried out in collaboration with Hanbat National University (Prof. Seongju Kim) and UNIST (Prof. Dongyun Kam).

  • Title: Statistically Resolving Thickness-Dependent Electrical Characteristics in Multilayer-MoS2 Transistors (link)

The study combines optical-intensity-based layer identification and algorithmic flake filtering to enable large-scale statistical analysis of multilayer MoS2 transistor behavior.

Join Us

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I/O Circuit Design for Multi-Chip Systems

Design and Benchmark (DB) or Component Packaging (CP)

This position focuses on the design of IO circuits — particularly logical PHY for die-to-die (D2D) interconnects — that form the backbone of future...

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VCT based Oxide DRAM

Technology Development (TD), Memory

The Memory Team focuses on oxide-semiconductor-based 2T0C DRAM, pursuing an integrated research framework that spans device architecture, fabrication processes, materials, circuits, and system-level design...

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Agent AI for Semiconductor System

개별연구 학생 (Undergraduate Internship)

This position focuses to establish a next-generation AI-native semiconductor design framework that enables integrated optimization across the Device–Circuit–Package–System stack. It includes AI-based standard cell...

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High Performance Logic Devices

Technology Development (TD), Logic

This position focuses on advanced CMOS technology development by investigating low-dimensional (2D/1D) transistors through experiments and TCAD simulations. The research extends device concepts to...

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Standard Cell Design and Benchmarking for 3D-Stacked FETs

Design and Benchmark (DB), DTCO

This position focuses on evaluating and abstracting the physical characteristics of silicon 3D-stacked FETs and novel-material devices from the standard-cell perspective. Building on this...

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System-Level Benchmarking of Advanced Devices and Packaging Technologies

Design and Benchmark (DB), STCO

This position focuses on system-level benchmarking of advanced devices and packaging technologies. The candidate will work on evaluating the performance, energy efficiency, and scalability...

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Advanced Packaging Technologies

Components and Packaging (CP), Packaging

This position focuses on integrated electrical, mechanical, and thermal design, experimentation, measurement, and development for high-speed signal transmission based on advanced packaging building-block technologies....

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