This position focuses on the design of IO circuits — particularly logical PHY for die-to-die (D2D) interconnects — that form the backbone of future chiplet and multi-chip systems. Building on the lab’s research in advanced packaging, interposers, and 3D-stacked architectures, you will design and validate IO circuit blocks that bridge the physical channel (interposer / package) and chip-level architecture, enabling scalable composition of heterogeneous dies into a single system. The role works in close coordination with the packaging team on signal/power integrity and with the design and benchmark team on system-level chiplet evaluation.

The Memory Team focuses on oxide-semiconductor-based 2T0C DRAM, pursuing an integrated research framework that spans device architecture, fabrication processes, materials, circuits, and system-level design to realize high-density, high-reliability, and low-power memory and computing platforms. In particular, we investigate vertical channel transistors (VCTs) as a core device platform to enable next-generation three-dimensional stacked memory and AI-oriented CIM/PIM architectures.

This position focuses to establish a next-generation AI-native semiconductor design framework that enables integrated optimization across the Device–Circuit–Package–System stack. It includes AI-based standard cell design and autonomous semiconductor measurement systems for 3DIC environments, RF power amplifier and impedance matching circuit design considering RF packaging effects, neural compact model-based readout circuit design for vertical-channel DRAM and gain-cell memory, and AI-enhanced performance prediction simulators for multi-chip (chiplet) systems.

This position focuses on advanced CMOS technology development by investigating low-dimensional (2D/1D) transistors through experiments and TCAD simulations. The research extends device concepts to logic architectures enabling standard cell height scaling (e.g., GAA, CFET), and evaluates power, performance, and area (PPA) from device to standard-cell and chip levels within a Design Technology Co-Optimization (DTCO) framework.

This position focuses on evaluating and abstracting the physical characteristics of silicon 3D-stacked FETs and novel-material devices from the standard-cell perspective. Building on this foundation, the role quantitatively investigates the PPA (Power, Performance, Area) gains achievable when advanced and 3D-stacked CMOS logic (e.g., GAA, CFET, FlipFET) and BEOL-compatible devices are integrated and stacked. Ultimately, based on these analyses, the position aims to propose new directions for three-dimensional integration and an application roadmap that can extend scaling beyond the limits of CMOS downscaling.

This position focuses on system-level benchmarking of advanced devices and packaging technologies. The candidate will work on evaluating the performance, energy efficiency, and scalability of emerging semiconductor devices and 3D packaging solutions in the context of real-world applications. This includes developing benchmarks that reflect the demands of AI workloads and other high-performance computing tasks, as well as analyzing how different device and packaging innovations impact overall system performance. The role involves close collaboration with device researchers, circuit designers, and architects to ensure that benchmarking efforts are aligned with the latest technological advancements.

This position focuses on integrated electrical, mechanical, and thermal design, experimentation, measurement, and development for high-speed signal transmission based on advanced packaging building-block technologies. You will participate in experiment- and simulation-driven research on high-speed interconnects and packaging technologies for next-generation semiconductor systems.