Join Our Lab
Our lab aims to develop core semiconductor technologies for next-generation AI hardware systems. To achieve this, we take a multidisciplinary approach—centered on Electrical Engineering and integrated with Mechanical Engineering, Materials Science, and Chemical Engineering—to research integrated semiconductor technologies that connect devices, packaging, and systems.
Our research proceeds in two main directions. First, we focus on Monolithic and Heterogeneous 3D IC technologies. For this, we develop 3D IC logic and memory devices alongside 3D IC design methodologies for high-performance, low-power computing, also known as DTCO (Design-Technology Co-Optimization). Second, we focus on advanced semiconductor packaging process technologies and multi-chip system design and evaluation technologies, also known as STCO (System-Technology Co-Optimization). Through this, we are developing scalable platforms that integrate various semiconductor chips to implement ultra-high-bandwidth and high-performance computing systems. By bridging device innovation, packaging technology, and system design, our lab strives to present a new paradigm for next-generation AI hardware and heterogeneous integrated computing systems.
Our lab is looking for positive and self-motivated students and researchers. We particularly value a strong sense of ethics, collegiality, a passion for research, and a healthy, independent attitude.
Our research fields cover a wide range of areas, including:
- Logic and memory transistors (2D TMD, CNT for logic / oxide semiconductors for DRAM)
- Monolithic 3D (M3D) systems (3D IC design and PPA evaluation)
- Advanced semiconductor packaging
- Heterogeneous multi-chip systems (package-level digital architecture, system evaluation)
In our lab, researchers from diverse backgrounds—such as Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, Chemistry, and Physics—are working together.
In particular, I am highly interested in building an Agentic AI research assistant system that can comprehensively utilize the diverse data generated during recent research processes. Many companies in Silicon Valley have already integrated this into their workflows, transitioning a wide range of tasks over to AI, from coding to the analysis of massive physical datasets. Accordingly, our lab is looking for researchers to build a new type of device and packaging research environment where AI and humans collaborate. If you dream of pursuing this kind of future-oriented research, please feel free to contact me at any time.
Currently, we give priority to applicants for the Ph.D. or MS-Ph.D. integrated programs who can make a long-term commitment. If you are interested, please send your CV, academic transcripts, and research activity materials (papers, projects, etc.) to my email (jmkwon@kaist.ac.kr).
※ Please note that as of the Spring semester of 2026, the lab has relocated to the School of Electrical Engineering in KAIST and the Department of AI Systems in KAIST.
Open Roles
High Performance Logic Devices
Logic
This position focuses on advanced CMOS technology development by investigating low-dimensional (2D/1D) transistors through experiments and TCAD simulations. The research extends device concepts to logic architectures enabling standard cell height scaling (e.g., GAA, CFET), and evaluates power, performance, and area (PPA) from device to standard-cell and chip levels within a Design Technology Co-Optimization (DTCO) framework.
VCT based Oxide DRAM
Memory
The Memory Team focuses on oxide-semiconductor-based 2T0C DRAM, pursuing an integrated research framework that spans device architecture, fabrication processes, materials, circuits, and system-level design to realize high-density, high-reliability, and low-power memory and computing platforms. In particular, we investigate vertical channel transistors (VCTs) as a core device platform to enable next-generation three-dimensional stacked memory and AI-oriented CIM/PIM architectures.
Standard Cell Design and Benchmarking for 3D-Stacked FETs
Design and Benchmark
This position focuses on evaluating and abstracting the physical characteristics of silicon 3D-stacked FETs and novel-material devices from the standard-cell perspective. Building on this foundation, the role quantitatively investigates the PPA (Power, Performance, Area) gains achievable when advanced and 3D-stacked CMOS logic (e.g., GAA, CFET, FlipFET) and BEOL-compatible devices are integrated and stacked. Ultimately, based on these analyses, the position aims to propose new directions for three-dimensional integration and an application roadmap that can extend scaling beyond the limits of CMOS downscaling.
System-Level Benchmarking of Advanced Devices and Packaging Technologies
Design and Benchmark
This position focuses on system-level benchmarking of advanced devices and packaging technologies. The candidate will work on evaluating the performance, energy efficiency, and scalability of emerging semiconductor devices and 3D packaging solutions in the context of real-world applications. This includes developing benchmarks that reflect the demands of AI workloads and other high-performance computing tasks, as well as analyzing how different device and packaging innovations impact overall system performance. The role involves close collaboration with device researchers, circuit designers, and architects to ensure that benchmarking efforts are aligned with the latest technological advancements.
Advanced Packaging Technologies
Components and Packaging
This position focuses on integrated electrical, mechanical, and thermal design, experimentation, measurement, and development for high-speed signal transmission based on advanced packaging building-block technologies. You will participate in experiment- and simulation-driven research on high-speed interconnects and packaging technologies for next-generation semiconductor systems.
Agent AI for Semiconductor System
개별연구 학생 (undergraduate)
This position focuses to establish a next-generation AI-native semiconductor design framework that enables integrated optimization across the Device–Circuit–Package–System stack. It includes AI-based standard cell design and autonomous semiconductor measurement systems for 3DIC environments, RF power amplifier and impedance matching circuit design considering RF packaging effects, neural compact model-based readout circuit design for vertical-channel DRAM and gain-cell memory, and AI-enhanced performance prediction simulators for multi-chip (chiplet) systems.