Design IO circuit blocks — including logical PHY for D2D, parallel/serial link IOs, driver/receiver and clocking circuits — targeting next-generation chiplet and multi-chip systems.
Characterize signal integrity, power integrity, and timing under realistic packaging and interposer environments, in close coordination with the lab’s packaging research.
Develop link-level modeling and design methodologies that connect circuit-level trade-offs (equalization, clocking, ESD, termination, driver/receiver topology) with package- and interposer-level constraints (channel response, crosstalk, PDN).
Collaborate with packaging researchers (interposer / RF channel), device-and-cell researchers (advanced CMOS, PPA), and architecture researchers (system-level chiplet benchmarking) so that IO design choices align with end-to-end system goals.
Who we are looking for
Candidates with strong interest in IO circuit design and chiplet / multi-chip system integration.
Undergraduate or graduate students in Electrical Engineering or Semiconductor Engineering who have taken courses in analog/digital circuit design, signals and systems, and semiconductor devices.
Candidates with academic or hands-on experience in IO circuit design — including D2D, SerDes, parallel link, or other high-speed IO blocks — or strong motivation to work in this area.
Familiarity with circuit simulation tools (e.g., Cadence Virtuoso, HSPICE), and/or EM/channel simulation tools (e.g., HFSS, CST) is a plus.
Interest in bridging circuits, packaging, and architecture, and in working closely with neighboring teams across the device–cell–package–system stack.
Candidates who can define design problems clearly, derive logical solution strategies, and engage in constructive technical discussions.
Strong attention to detail in design, simulation, and measurement validation.