What you will do
You will:
- Develop system-level benchmarking methodologies that translate device- and cell-level characteristics (e.g., PPA results from advanced and 3D-stacked CMOS logic) into chip- and system-level metrics for performance, energy efficiency, and scalability.
- Build workload-driven evaluation frameworks that reflect the demands of AI training/inference and other high-performance computing tasks, and use them to quantify how emerging devices and 3D/advanced packaging technologies impact end-to-end system performance.
- Model and analyze the system-level implications of advanced packaging building blocks (e.g., high-speed interconnects, 2.5D/3D integration, chiplet-based architectures), in close coordination with the cell-design and packaging research within the group.
- Collaborate with device researchers, circuit designers, and architects to ensure that benchmark assumptions, abstractions, and figures of merit remain aligned with the latest technological advancements, and feed the resulting insights back into DTCO and STCO decisions.
Who we are looking for
- Candidates with strong interest in system-level benchmarking, computer architecture, and DTCO/STCO.
- Graduates in Electrical Engineering, Computer Science/Engineering, or Semiconductor Engineering who have taken courses in computer architecture, digital systems, and semiconductor devices/circuits.
- Candidates with academic or hands-on experience with, or strong motivation to learn, architectural simulators (e.g., gem5), workload characterization tools, or system-level performance/power modeling frameworks.
- Individuals interested in bridging multiple abstraction levels — from devices and standard cells, through circuits and packaging, up to chip- and system-level architectures.
- Candidates who can define benchmarking problems clearly, derive logical evaluation methodologies, and translate raw measurements into actionable design insight.
- Individuals who can communicate effectively with collaborators across device, circuit, packaging, and architecture domains, and engage in constructive technical discussions.
- Candidates who, based on a broad research perspective, actively seek and propose new evaluation approaches for emerging devices, 3D-stacked logic, and advanced packaging technologies.
- Individuals who can holistically evaluate trade-offs across process, device, circuit, packaging, and architecture, and concretize new ideas with data and logic—connecting them to feasibility through modeling, simulation, and benchmarking.