We develop oxide-semiconductor-based vertical-channel transistor processes and device structures, targeting 3D stacking for highly integrated on-chip memory.
We analyze and improve the reliability of vertical-channel transistors from both device-structure and process perspectives, and systematically correlate device degradation mechanisms with DRAM operation, including retention and disturbance behaviors.
We design peripheral circuits optimized for DRAM arrays based on oxide-semiconductor VCTs, and perform cell-level operation analysis using TCAD mixed-mode simulations.
We establish compact models that capture the physical characteristics of oxide-semiconductor transistors and apply them to array-level circuit simulations, further extending the framework to PIM and CIM architectures to evaluate AI-computing applicability.
Through ALD-based oxide-semiconductor channel engineering, we optimize high-performance characteristics and channel reliability required for DRAM operation.
Who we are looking for
Graduates in Electrical Engineering, Materials Science and Engineering, or Semiconductor Engineering who have completed courses in semiconductor devices and fabrication, or who demonstrate a strong interest in memory-oriented transistors and fabrication processes.
Undergraduate students or graduates in Electrical Engineering who have taken courses related to semiconductor devices and integrated circuits (ICs), or who possess a solid foundational understanding of these topics.
Candidates who are interested in modeling and designing systems across multiple levels, from device physics to memory cells and peripheral circuits.
Candidates with academic or hands-on experience in memory circuit design — including sense amplifiers, decoders, and other peripheral circuits, or PIM/CIM circuits — or strong motivation to work in this area.
Researchers who can define problems and develop logical solution strategies
Applicants who value precision in experimentation and data analysis.