• Title: Vertical-Die (V-die) 3.5D Integration for Cool Ultrahigh-Bandwidth Memory Systems

Papers submitted by Heesoo Yang and Hyeongjun Kim were accepted to the IEEE Symposium on VLSI Technology and Circuits (VLSI) 2026. The results were produced through collaboration with Hanbat National University (Prof. Seongju Kim) and UNIST (Prof. Dongyun Kam).

• Title: Statistically Resolving Thickness-Dependent Electrical Characteristics in Multilayer-MoS2 Transistors (link)

The study combines optical-intensity-based layer identification and algorithmic flake filtering to enable large-scale statistical analysis of multilayer MoS2 transistor behavior.

Guhyun Ho received the Graduate School Outstanding Thesis Award for research on oxide-semiconductor vertical-channel-transistor-based 2T0C gain-cell memory.

• Title: Advances and future challenges in monolithic 3D integrated logic, power, and optoelectronics technologies for tightly interconnected intelligent systems (link)

The article presents a broad perspective on monolithic 3D integration and optoelectronic co-integration for next-generation AI and HPC systems, from materials to system-level design.

• Title: Indium Tin Oxide Vertical Channel Transistors for Scaled 4F2 2T0C Gain Cell Memory with Etched Sidewall Cleaning (link)

Oxide-based vertical-channel transistors can enable 4F2-class DRAM cells, but hole-etch residues contaminate sidewalls and limit scaling. This work identifies the degradation mechanism and demonstrates strong recovery through post-etch wet cleaning.

• Title: Development of Silver EHD Jet Printing Design Rules for Reliable RF Component Fabrication

Hyeongjun Kim received a Best Poster Award at the International Symposium on Microelectronics and Packaging (ISMP) 2025.

• Project: V-die integrated packaging technologies for ultra-high-bandwidth AI accelerators
• Organization/Program Office: Samsung Electronics / Samsung Future Technology Incubation Center
• Participation/Period: Single-institution project / 2025.12.01 - 2030.12.31

Our lab was selected for the Samsung Future Technology Program to develop vertically integrated V-die packaging technologies for scalable AI accelerator systems.

• Title: Addressing Gain-Bandwidth Trade-off by Electrolyte-All-Around Organic Electrochemical Transistors (link)

The study introduces an electrolyte-surround architecture to improve ion transport dynamics and overcome the gain-bandwidth trade-off in OECTs.

• Thermal Evaluation and Comparison of CAA and GAA Indium Tin Oxide Vertical Channel Transistors
• Monolithic 3D Integration of III-V HEMTs on Glass Using Ultra-Thin Dielectric Bonding Layer
• Active BSCDN Benchmark Framework with Backside-Compatible CNFET Logic Technology

Three papers submitted by our students were accepted simultaneously to IEEE IEDM 2025. The work was conducted in collaboration with Stanford University (Prof. Eric Pop, Prof. H.-S. Philip Wong), KAIST (Prof. Sanghyeon Kim), and UNIST (Prof. Heechun Park).

Seunghun Baek, Hyeongjun Kim, and Heesoo Yang were selected for the NRF Master’s Research Fellowship program.

The program supports full-time master’s students by providing one year of funding for thesis research and early-stage researcher development.

Dr. Seongju Kim was appointed as an Assistant Professor in the Department of Convergence and Creativity at Hanbat National University.

• Project: Development of microwave signal generation and processing hardware for quantum system control
• Ministry/Agency: Ministry of Science and ICT / National Research Foundation of Korea (NRF)
• Participation/Period: Consortium project / 2025.07.01 - 2027.12.31

Our lab was selected for the Quantum Core Technology Development Program to develop an FPGA-based RF front-end platform with integrated LO, filtering, amplification, and control modules.

• Project: Development of AI- and 3D-printing-based high-thermal-performance semiconductor packaging technologies
• Program: NRF Postdoctoral Growth Support Program (Ministry of Education / NRF)

Dr. Haksoon Jung was selected for the NRF Postdoctoral Growth Support Program, which supports postdoctoral researchers with multi-year funding and mentoring toward independent research careers.

• Dr. Seongju Kim: Reinforcement-learning-based optimal cooling-channel design for advanced semiconductor packaging
• Dr. Haksoon Jung: 3D-printed organic fan-out substrates for advanced semiconductor packaging

Both researchers received top awards at the 2025 KIEEM Summer Conference.

• Title: Top-Gate Oxide Semiconductor FETs for Reliable 2T0C Read/Write Operation with Reduced Capacitive Coupling (link)

Minho Park received a Best Paper Award at KCS 2025.

• Nahyeon Kim: 3D-Printed Quasi-Coaxial Through-Hole Embedded Substrate for Antenna-in-Package Applications
• Hyeongjun Kim: Fabrication of RF Transmission Lines and Antenna Using Electrohydrodynamic Inkjet Printing

Two students from our lab received Best Presentation Awards at KFPE 2025.

• Title: 3D-Printed Antenna-in-Package Substrates with Quasi-Coaxial Through-Vias for 5G-Advanced Applications

Nahyeon Kim received an On-site Best Poster Award at the Korean Conference on Semiconductors (KCS) 2025.

• Title: Back-end-of-line-compatible passivation of sulfur vacancies in MoS2 transistors using electron-withdrawing benzenethiol (link)

This work introduces a BEOL-compatible sulfur-vacancy passivation strategy for MoS2 transistors and demonstrates strong performance and reliability improvements through process-compatible defect engineering.

• Title: Fabrication of top-gate MoS2 FETs via gate-dielectric seed-layer optimization

Sumin Hong received a Best Presentation Award in the graduate student oral session at the KFPE 2024 Fall Conference.

Prof. Jimin Kwon received the 2024 Young Scholar Award from the Korean Society of Flexible and Printed Electronics (KFPE) in recognition of outstanding contributions as an emerging researcher.

• Project: Printed organic electrochemical transistor technologies for next-generation communication systems
• Program: NRF Domestic Postdoctoral Fellowship

Dr. Yongwoo Lee was selected for the NRF Domestic Postdoctoral Fellowship program, which provides opportunities for Ph.D. researchers to continue advanced research at leading institutions in Korea.

Students Guhyun Ho, Hyeonjin Lee, and Nahyeon Kim were selected for the NRF Master’s Research Fellowship program.

The program provides full-time master’s students with one year of support to conduct thesis research and strengthen early-stage research capability.

• Title: Dual-gate carbon nanotube thin-film transistors with printed channel and passivation interlayer on plastic foil (link)

This work reports high-performance printed CNT transistors using a dual-gate architecture and polymer interlayer engineering to improve gate controllability and suppress leakage. The study demonstrates a scalable route toward reliable printed electronics for advanced circuits.

• Title: Stabilizing Schottky junction in conjugated polymer diodes enables long-term reliable radio-frequency energy harvesting on plastic (link)

Long-term diode stability is critical for wireless power transfer in wearable systems. We identified unstable chemical bonding at the semiconductor-cathode interface as the key degradation mechanism in flexible organic diodes. Through comprehensive analysis and interlayer engineering, we demonstrated a Schottky diode with stable operation over several months. This work was supported by NRF and IITP.

Related coverage: ETNews, Yonhap News

• Title: Micro-3D-printed packaging substrates with embedded through holes for organic interposers (link)

Semiconductor system performance is increasingly determined by how chips are interconnected through packaging technology. In this work, we proposed a new process to fabricate packaging substrates with through-holes using micro 3D printing. Fine through-holes were formed without etching, reducing process complexity while increasing design flexibility. We also developed a reliable inner-hole metallization process, demonstrating broad applicability to advanced packaging substrates. This work was supported by NRF and IITP.

• Project: Core technology development for 3D-printing-based semiconductor packaging

Our lab was selected for the National Semiconductor Laboratory core technology support program in advanced semiconductor packaging. A total of 9 labs (first half) and 10 labs (second half) were selected nationwide, and this was the first selection from UNIST. The project is supported by the 3D Printing Center and Ulsan Metropolitan City.

Related coverage: Seoul Economic Daily, UNIST News Center