What you will do
You will: We model semiconductor device characteristics to enable circuit-operation simulations, and define cell-level operating behavior by incorporating parasitic components that arise within the cell. We propose novel structures that can leverage three-dimensional space within the cell (e.g., CFET) and conduct research to analyze the PPA (Power, Performance, Area) gains achievable at the circuit-block or system level. We simulate integration strategies for applying monolithic 3D (M3D) structures and quantify the benefits upon adoption. By defining process technologies that reflect physical characteristics and leveraging 3D-stacked circuit design techniques, we pursue such evaluations and optimizations.
Who we are looking for
Candidates with strong interest in DTCO (Design and Technology Co-Optimization). Graduates in Electrical Engineering or Semiconductor Engineering who have taken courses in semiconductor engineering, electronic circuits, and digital circuit design, or candidates interested in next-generation 3D semiconductor structures and cell design, as well as M3D-integrated systems. Candidates with academic or hands-on experience learning/using TCAD, Virtuoso, and/or SPICE. Individuals interested in modeling and designing across multiple levels—from device physics and standard cells to peripheral circuits. Researchers who can define problems clearly and derive logical solution strategies. Individuals who can articulate issues that arise during research, design structured approaches to resolve them, and engage in constructive discussions. Candidates who, based on broad research perspective and a challenging problem-solving mindset, actively seek and propose new process and circuit technologies. Individuals who can holistically evaluate trade-offs across process, device, circuit, and architecture, define alternatives beyond conventional approaches, and concretize new ideas with data and logic—connecting them to feasibility through design, modeling, and validation.