Seongju Kim

Seongju Kim

Mar 2025 - Aug 2025

  • Postdoctoral Researcher
  • UNIST Nanoelectronics and Advanced Packaging Lab (UNL) Postdoctoral Researcher, CP Team
  • Thermal Management of Advanced Packaging by Machine Learning

Current: Assistant Professor, Department of Creative Convergence Engineering, Hanbat National University

BIO

Dr. Seongju Kim was a postdoctoral researcher in UNIST Nanoelectronics and Advanced Packaging Lab (UNL) from March to August 2025. His research focused on thermal management of advanced packaging by machine learning. During his time in the lab, Dr. Kim actively engaged with students as a dedicated mentor. He generously shared his expertise by teaching foundational artificial intelligence concepts to lab members, and he took charge of thermal simulations and analyses across multiple projects, bringing valuable diversity to the lab's research. Beyond his meticulous work ethic and exceptional technical skills, he is remembered as a wonderful colleague. His unwavering positive mindset and warm interpersonal skills made him a constant source of encouragement and energy to everyone around him.

Career

  • Assistant Professor / Department of Creative Convergence Engineering, Hanbat National University (Sep 2025 - present)
  • Postdoctoral Researcher / Department of Electrical Engineering, UNIST (Mar 2025 - Aug 2025)

Education

  • PhD / Department of Materials Science and Engineering, POSTECH (Sep 2022 - Feb 2025)
  • MS / Department of Mechanical Engineering, POSTECH (Mar 2018 - Feb 2020)
  • BS / Department of Mechanical Engineering, Ajou University (Mar 2011 - Feb 2018)

Publications in Lab

Journal

  1. Statistically resolving thickness-dependent electrical characteristics in multilayer-MoS2 transistors
    Co-author · Advanced Functional Materials (Early access), 2026
  2. 3D active-matrix multimodal sensors arrays for independent detection of pressure and temperature
    Co-author · Science Advances 11 (3), 2025
  3. Spatiotemporal measurement of arterial pulse waves enabled by wearable active-matrix pressure sensor arrays
    Co-author · ACS Nano 16 (1), 2022
  4. Parylene-based double-layer gate dielectrics for organic field-effect transistors
    Co-author · ACS Applied Materials & Interfaces 10 (44), 2018

Conference

  1. Vertical-die (V-die) 3.5D integration for cool ultrahigh-bandwidth memory systems
    Co-author · 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (Accepted)
  2. Microchannel-Embedded 3D-Printed Ceramic Substrates for Liquid-Cooled Power Module Packaging
    Co-author · 2026 76th Electronic Components and Technology Conference (ECTC)
  3. Active BSCDN benchmark framework with backside-compatible CNFET logic technology
    Co-author · 2025 71th IEEE International Electron Devices Meeting (IEDM)
  4. Monolithic 3D integration of III-V HEMTs on glass using ultra-thin dielectric bonding layer: A high-frequency and low-loss active glass platform for sub-THz applications
    Co-author · 2025 71th IEEE International Electron Devices Meeting (IEDM)
  5. Quasi-coaxial through-hole integrated additively manufactured antenna-in-package lid substrates
    Co-author · 2025 75th Electronic Components and Technology Conference (ECTC)
  6. 3D printed fanout interposer substrates with curved through-holes for rapid prototyping of advanced packaging
    Co-author · 2025 75th Electronic Components and Technology Conference (ECTC)