Hyeonho Gu

Hyeonho Gu

July 2023 - Current

  • MS Student
  • UNIST Nanoelectronics and Advanced Packaging Lab (UNL) MS Student, TD Team
  • Student representative (Jan 2023 - Dec 2025)
  • Vertical-Channel OS FET for M3D Memory, M3D FET Logic

Current: Post MS Researcher, KAIST

BIO

Mr. Hyeonho Gu was a Master's student in the UNIST Nanoelectronics and Advanced Packaging Lab (UNL) from July 2023 to February 2026. His research centered on oxide semiconductor-based memory devices — pioneering indium tin oxide (ITO) vertical-channel transistors for monolithic 3D (M3D) memory integration and capacitor-less 2T0C gain-cell memory, areas that have since become a cornerstone of the lab's research direction. His contributions to the field are reflected in a first-authored publication in IEEE Electron Device Letters and a co-authored paper in ACS Nano. Beyond his own achievements, Hyeonho played a defining role in shaping the lab's technical foundation — generously sharing his deep process expertise, guiding junior members through complex fabrication challenges, and building the experimental backbone that the lab continues to build upon. His dedication, quiet leadership, and the genuine warmth he brought to every interaction have left an impression that will endure long after his time at UNL. He is currently pursuing his career as a Post-MS Researcher in the Department of Electrical Engineering at KAIST.

Career

  • Post MS Researcher / Department of Electrical Engineering, KAIST (Apr 2026 - present)
  • Post MS Researcher / Department of Electrical Engineering, UNIST (Mar 2026)

Education

  • MS / Department of Electrical Engineering, UNIST (Sep 2023 - Feb 2026)
  • BS / Department of Electrical and Information Engineering, SeoulTech (Mar 2017 - Feb 2023)

Publications in Lab

Journal

  1. Back-end-of-line-compatible passivation of sulfur vacancies in MoS2 transistors using electron-withdrawing benzenethiol
    Co-author · ACS Nano 19 (6), 2025
  2. Indium tin oxide vertical channel transistors for scaled 4F2 2T0C gain cell memory with etched sidewall cleaning
    First author · IEEE Electron Device Letters 47 (4), 2026
  3. Wafer-scale non-ferroelectric κ-phase 2D In2Se3 transistors
    Co-author · Nature Communications (early access)
  4. Oxygen-tunnel-engineered indium tin oxide vertical channel transistors enabling high-performance embedded memory for monolithic 3D integration
    First author · under review

Conference

  1. Thermal evaluation and comparison of CAA and GAA indium tin oxide vertical channel transistors
    Co-author · 2025 71th IEEE International Electron Devices Meeting (IEDM)