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KAIST Device-to-System Integration Lab (DSIL)

Our lab aims to develop core semiconductor technologies for next-generation AI hardware systems. To achieve this, we take a multidisciplinary approach—centered on Electrical Engineering and integrated with Mechanical Engineering, Materials Science, and Chemical Engineering—to research integrated semiconductor technologies that connect devices, packaging, and systems.

Our research fields cover a wide range of areas, including:

  • Logic and memory transistors (2D TMD, CNT for logic / oxide semiconductors for DRAM)
  • Monolithic 3D (M3D) systems (3D IC design and PPA evaluation)
  • Advanced semiconductor packaging
  • Heterogeneous multi-chip systems (package-level digital architecture, system evaluation)

Contact Us

Currently, we give priority to applicants for the Ph.D. or MS-Ph.D. integrated programs who can make a long-term commitment. If you are interested, please send your CV, academic transcripts, and research activity materials (papers, projects, etc.) to my email (jmkwon@kaist.ac.kr).

Latest News

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  • Dr. Yongwoo Lee has been selected for the Independent Research Track of the Postdoctoral Researcher Growth Support Program, funded by the Ministry of Education and the National Research Foundation of Korea (NRF).

-Project Title: Development of Core Technologies for Highly Reliable Glass Substrate-Based Packaging with Embedded mmWave GaN RF PAs for Physical AI Humanoids. (link)

This program supports promising postdoctoral researchers in conducting innovative and challenging research under the mentorship of a faculty member, enabling them to grow into independent researchers. The selected researcher will receive KRW 60 million annually for three years.

Title: Monolithic 3D-Integrated All-Solid Ion-Gated Carbon Nanotube Transistors With Tunable Ionic Conductance for Multi-Timescale Reservoir Computing (link)

In this study, we propose all-solid ion-gated transistors (sIGTs) with semiconducting carbon nanotube (CNT) channels that enable wide-range engineering of ionic dynamics while remaining fully compatible with scalable thin-film processing.

By precisely tuning the ionic content and thickness of the solid ionogel down to the sub-micron regime, ionic time constants ranging from microseconds to milliseconds were achieved within an identical device geometry.

Electrical impedance spectroscopy (EIS) and small-signal analysis were used to systematically reveal the relationship between ionic conductance and frequency-dependent device response, and uniform, reliable device characteristics were demonstrated at up to 4-inch wafer scale as well as on flexible substrates.

At the system level, two CNT sIGT layers with distinct ionic dynamics were vertically integrated through monolithic 3D (M3D) stacking to realize a dual-timescale physical reservoir capable of classifying time-varying input signals using a single readout layer.

This work demonstrates the potential of sIGTs as a scalable hardware platform for multi-timescale signal processing in neuromorphic computing.

This research was supported by the National Research Foundation of Korea (NRF), the Korea Planning & Evaluation Institute of Industrial Technology (KEIT), the Ministry of Science and ICT (MSIT), and the Ministry of Trade, Industry and Energy (MOTIE).

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